COA Unit 2 - Processor Design & Memory Organization

1. Accumulator-Based Organization

Definition: CPU uses single special register (Accumulator/ACC) for all arithmetic & logical operations. Operands from ACC, result stored back in ACC.

Characteristics:

• Simple hardware
• Fewer registers
• 1-address instructions (ADD X → ACC = ACC + X)
• Good for small/simple processors

2. General Register Organization

Definition: Multiple general-purpose registers (R0, R1, R2…) used for storing operands and results instead of one accumulator.

Characteristics:

• Flexibility
• Faster execution
• Supports 2-address & 3-address instructions
• Widely used in modern CPUs
• Example: ADD R1, R2, R3 → R1 = R2 + R3

3. Stack Organization

Definition: Stack-based CPU uses LIFO (Last-In-First-Out) stack for storing operands. Instructions don't need explicit operands.

Characteristics:

• 0-address instructions
• PUSH and POP operations
• Operands automatically from stack top
• Used in expression evaluation

Example:
PUSH A
PUSH B
ADD (pops A and B, pushes result)

4. RISC Architecture (Reduced Instruction Set Computer)

Definition: CPU design with small set of simple, fast, fixed-length instructions.

Key Features:

• Simple instructions
• One instruction per cycle
• Large number of registers
• Hardwired control unit
• Load-store architecture
• Faster execution
• Examples: ARM, MIPS, RISC-V

5. CISC Architecture (Complex Instruction Set Computer)

Definition: CPU design with large set of complex instructions performing multiple tasks in one instruction.

Key Features:

• Complex multi-cycle instructions
• Variable-length instructions
• More addressing modes
• Microprogrammed control unit
• Smaller number of registers
• Examples: Intel x86 processors

RISC vs CISC Comparison

Feature	RISC	CISC
Instructions	Simple	Complex
Execution	Single cycle	Multi-cycle
Control Unit	Hardwired	Microprogrammed
Registers	More	Fewer
Code Size	Large	Small
Speed	Faster	Slower

1. Hardwired Control Unit

Definition: Control signals generated by fixed hardware circuits (logic gates, flip-flops).

Characteristics:

• Very fast
• Difficult to modify
• Used in RISC processors
• High performance

2. Microprogrammed Control Unit

Definition: Control signals generated using microinstructions stored in control memory (like small program controlling CPU).

Characteristics:

• Easier to design
• Simple to modify (change microcode)
• Used in CISC processors
• Slower than hardwired

Hardwired vs Microprogrammed

Feature	Hardwired	Microprogrammed
Speed	Fast	Slower
Modification	Difficult	Easy
Cost	Higher	Lower
Flexibility	Low	High
Used In	RISC	CISC

1. Memory Hierarchy

Definition: Structure arranging memory levels based on speed, cost, and size.

Order (Fastest → Slowest):

1. Registers (fastest, smallest)
2. Cache Memory
3. Main Memory (RAM)
4. Secondary Memory (SSD/HDD)
5. Tertiary Storage (Backup devices)

Goal: Low cost + High speed

2. Main Memory (RAM & ROM)

RAM (Random Access Memory):

• Volatile
• Read/Write
• Used for active programs
• Types: SRAM, DRAM

ROM (Read Only Memory):

• Permanent
• Stores firmware
• Non-volatile

3. Auxiliary Memory

Long-term storage: HDD, SSD, Pendrive, CD/DVD. Larger size but slower.

4. Associative Memory (Content Addressable Memory)

Definition: Memory where data accessed by content, not address. Allows parallel searching.

Used in: Cache, TLB, Networking devices

5. Cache Memory

Definition: High-speed memory between CPU and main memory to reduce access time.

Levels: L1 (fastest) → L2 → L3 (largest)

6. Cache Mapping Techniques

1. Direct Mapping:

Each memory block maps to exactly one cache line. Simple but many conflicts.

2. Associative Mapping:

Block stored in any cache line. Flexible but expensive.

3. Set-Associative Mapping:

Cache divided into sets; block goes in any line of set. Balance of speed & cost.

7. Cache Replacement Algorithms

Used when cache is full:

• FIFO – First block loaded is removed

• LRU – Least recently used block replaced

• LFU – Least frequently used block replaced

• Random – Random line replaced

8. Write Policies

Write-Through:

Write to cache & memory simultaneously. More reliable but slower.

Write-Back:

Write only to cache; write to memory later. Faster but needs dirty bit.

9. Virtual Memory

Definition: Technique giving illusion of large memory using secondary storage (disk) as RAM extension.

Features:

• Uses paging
• Allows running large programs
• Prevents memory overflow

10. Memory Management Unit (MMU)

Definition: Hardware unit converting logical addresses to physical addresses.

Functions:

• Paging
• Protection
• Address translation
• Handling virtual memory

Quick Revision - Key Points

🔹 CPU Organizations: Accumulator → single ACC | General Register → many registers | Stack → LIFO | RISC → simple, fast | CISC → complex, slow

🔹 Control Units: Hardwired → fast, fixed | Microprogrammed → slow, flexible

🔹 Memory Hierarchy: Registers → Cache → RAM → HDD/SSD (Fastest → Slowest)

🔹 Main Memory: RAM (volatile, read/write) | ROM (permanent, non-volatile)

🔹 Associative Memory: Search by content (CAM)

🔹 Cache Mapping: Direct | Associative | Set-Associative

🔹 Cache Replacement: FIFO, LRU, LFU, Random

🔹 Write Policies: Write-through (both) | Write-back (cache first)

🔹 Virtual Memory: Uses paging + MMU, extends RAM with disk

🔹 MMU Functions: Paging, Protection, Address translation, Virtual memory handling

✨ EXAM HALL MEIN: Yeh 10 points padhle + exam start! Good luck! 🚀

📑 Chapters

📚 COA Unit 2